Seagate announced its Pulsar SSD line on December 7 or 8 (depending on which version of the press release Google finds for you), allowing a show to drop that people had expected for more than a year. Pulsar drives use the familiar 2.5-inch HDD form factor and a SATA interface, making it easy to drop the drives into existing computer and server systems. Seagate’s Pulsar SSDs employ SLC (single-level cell) NAND Flash devices, which cost more per bit than MLC (multi-level cell) and TLC (three-level cell) NAND Flash devices. In exchange for the higher cost, you get more reliable memory, as was discussed in this blog a while back. (Check out “More than Moore: SLC, MLC, and TLC NAND Flash.”)

Seagate Pulsar SSD

The use of SLC NAND Flash underscores Seagate’s focus on enterprise-class storage for the SSD. There are at least two good reasons for Seagate’s enterprise focus. First, enterprise customers are more able to translate an SSD’s speed advantage over HDDs into dollars (as previously discussed in the blog entry “SSD TCO (Total Cost of Ownership”). Second, SSDs are a premium product with a premium price. Enterprise customers more easily accept the higher cost/Gbyte price tag attached to SSDs. Seagate’s Pulsar SSDs are available in storage capacities to 200 Gbytes and the SSDs achieve “a peak performance of up to 30,000 read IOPS and 25,000 write IOPS, 240MB/s sequential read and 200 MB/s sequential write” according to Seagate’s press release. The Pulsar drives have a 5-year limited warranty.

Micron Technology rolled out its RealSSD C300 less than a week before Seagate’s SSD announcement. The first glaringly obvious difference in Micron’s C300 SSD is that it sports a 6-Gbyte/sec SATA 6.0 interface. However, the faster interface alone will not boost performance (discussed earlier in this blog here) if the drive internals aren’t designed to sustain high transfer rates supported by SATA 6.0. To that end, Micron’s RealSSD C300 press release discloses the fact that the new Micron SSD “leverages a finely tuned architecture and high-speed ONFI 2.1 NAND Flash  to provide a whole new level of performance.” (ONFi, the Open NAND Flash interface, is discussed in this previous blog entry.) The result: a read throughput speed of up to 355MB/s and a write throughput speed of up to 215MB/s.

Compare those numbers to Seagate’s Pulsar and you’ll see that the Micron drive’s read throughput is nearly 50% faster but the write throughput is only 7.5% faster. Write throughput is one of the Achilles’ heels of SSDs. NAND Flash devices had an erase/write cycle that simply takes time.

Micron RealSSD C300

Micron’s C300 SSDs will be offered in 1.8-inch and 2.5-inch form factors, with both form factors supporting 128- and 256-Gbyte capacities. Micron is currently sampling the C300 SSD in limited quantities and expects to enter production in the first quarter of calendar 2010.

Both companies are making smart moves into the SSD market. Seagate, like Western Digital and its acquisition of SSD vendor SiliconSystems in March of this year, recognizes that it’s not in the HDD business—it’s in the storage business and SSD storage is hot right now. Micron, like Intel, sees SSDs as a value-added way to package and market it’s NAND Flash devices. Both companies have made very smart moves into the SSD market.

Both Intel and Micron are selling solid-state drives (SSDs) based on their most advanced Flash parts and so both companies have internal incentives to cut per-bit Flash costs as quickly as they can both to make their NAND Flash ICs competitive and to drive down the cost of their SSDs. Cost is now the biggest obstacle for SSDs in their quest to become mainstream storage devices.

Also according to this article, Micron Technology posted its first profit in 3 years during the period ending December 3, 2009 with sales worth $1.74 billion. The company’s NAND business rose 21% quarter over quarter and its DRAM business rose by as much as 50% during the same period. Good tidings indeed for Micron and the Flash business.

With IC lithographies approaching atomic limits—and our absolute inability to pattern transistors using fractional atoms that inevitably leads to the subsequent slowing of Moore’s-Law scaling—a third dimension starts looking mighty attractive. Just as cities started to build up towards the sky to fit more people and more businesses into limited downtown real estate, IC designers would dearly love to find easy ways to pack more transistors, more gates, and more bits into the same limited on-die real estate. One way to do this is to build circuits in layers. Intel and Numonyx will be discussing a new way to build nonvolatile phase-change memory (PCM) ICs using multiple layers in a few days at the IEDM conference in Baltimore, Maryland. But NAND Flash designers have already discovered another way to pack more bits into the same space by stuffing existing 2D memory cells with multiple bits. This approach also represents a way to circumvent 2D limits—to put NAND Flash bit capacity on a trajectory that is “more than Moore.”

Flash memory stores bits as charge trapped in a transistor’s floating gate, which is an isolated island of semiconductor surrounded by insulator. Electron tunneling drives the charge into the floating gate through where it *mostly* remains trapped until erased. (Sometimes, the electrons wander off by themselves or through a phenomenon called “read disturb.”) The electrons trapped in the floating FET gate act like a phantom negative voltage that prevents the transistor from conducting when read. This is the original mechanism developed for the NAND Flash memory by Dr. Fujio Masuoka while working for Toshiba circa 1980. It’s a simple binary use of trapped charge. When charge is trapped in the NAND Flash cell’s floating gate, the associated transistor will not conduct when read. When there are no trapped electrons, the transistor will conduct during a read operation. You get a simple binary response to the trapped charge or lack of trapped charge.

However, there’s an essential analog mechanism available here. The Flash memory can trap more or fewer electrons in the floating gate. The variable amount of charge can be measured by a fast A/D converter. If you store four different charge amounts on a floating gate (empty, quarter full, half full, three quarters full, and full) then you have essentially put two bits (four states) worth of information in one NAND Flash memory cell. If you can trap and measure eight charge levels of charge in a NAND Flash memory cell, then you have essentially put three bits worth of information into one NAND Flash memory cell. NAND Flash memories that store one bit/cell are called single-level cell (SLC) memory. Store two bits/cell and you have multi-level cell (MLC) memory. Store three bits per cell and you have three-level cell (TLC) memory (or 3BPC—three-bit/cell—memory using Micron Technology’s terminology).

Great! Why not pack two or three bits worth of information into every NAND Flash memory cell and essentially boost the NAND Flash chip’s memory capacity “for free?” Well, why not?

There are a few reasons why not. First, MLC and TLC NAND Flash memory is slower than SLC NAND Flash memory. You need more time for the on-chip A/D conversion circuitry to resolve the amount of charge stored in the selected cell. Second, there are more and more complex wear, reliability, and endurance issues with MLC and TLC NAND Flash memory than for SLC NAND Flash memory. One NAND Flash wearout mechanism involves permanently trapped charge and MLC and TLC NAND Flash memories are more susceptible to such failures because the exact amount of charge trapped by the tunneling process is far more critical when storing more bits per cell. A little permanently trapped charge can really mess things up.

Choosing between SLC, MLC, and TLC memory can be tricky. The choice involves several of your design criteria including the simple and obvious one (read/write latency requirements) and the more fuzzy ones (failure rate, reliability, and cycle endurance). In short, you cannot choose using a simple cost/bit analysis.

Finally, if you’d like a painless video intro to the world of SLC, MLC, and TLC or 3BPC NAND Flash memory concepts, here’s a 5-minute video from Micron Technology: