2x nm will happen – Currently, vendors are shipping 34nm NAND Flash memory in volume. That’s a tremendous engineering feat in itself. As reported in an earlier blog entry (“Intel, Micron striving to regain lead in NAND tech”), Intel and Micron Technology are apparently planning to ship NAND Flash devices based on 2x nm lithography (called 2x because it’s not yet clear if it’s 26nm, 25nm, 24nm, or 22nm). Lithography shrinks are a true race to the bottom. Features on chips have become so small that one or two atoms of difference from one part of a chip to another cause real changes in device characteristics. This phenomenon is called on-chip variation or on-chip variability (OCV) and it’s a tough problem to tackle, requiring the use of smarter on-chip circuitry to deal with the variation. (See “My Head Hurts, My Timing Stinks, and I Don’t Love On-Chip Variation” by Matt Weber.) The problems do not appear to be insurmountable and NAND Flash vendors currently leading the lithography derby appear intent on keeping that lead until it’s no longer possible.

SDDs will get bigger and faster – This prediction needs to be written, but it’s really a no-brainer. The “bigger” part of the prediction is based on the ever-increasing capacity of the NAND Flash chips used to make SSDs. They will get bigger, driven by economic forces far beyond SSD usage. USB Flash-memory drives are the big volume driver in this market and there’s always demand for more capacity there while the form factor emphasizes small and slim. Nowhere to go but more on-chip capacity. Number two driver is SD cards for cameras and camcorders, with the same forces at work. As for faster, it’s clear that SATA 6G is in the immediate future for SSDs. Marvel’s SATA 6G controller (see “Early Results Show SATA 6G Performance All Over the Map”) and Micron’s introduction this month of an SSD that exploits SATA 6G to good effect (see “New SSD Introductions from Seagate and Micron”) clearly point the way to faster SSD operation, once the internal architectural designs are aligned with the faster interface.

ONFi 2.1 gets big – ONFi stands for the “Open NAND Flash interface” and the ONFi organization (www.onfi.org) bills it as the fastest Flash interface on the planet. Hyperbole aside, ONFi supports transfer rates to 200 Mbytes/sec. and that’s speedy in anyone’s book. The ONFi Working Group was formed in May 2006 and currently has over 80 member companies including Hynix Semiconductor, Intel Corporation, Micron Technology, Inc., Numonyx, Phison Electronics Corporation, Sony Corporation and Spansion. Wanna fight those guys as a group?

MLC and TLC get big – It’s already happening. Several NAND Flash vendors already offer MLC (multi-level cell) and TLC (three-level cell) NAND Flash devices. They are working to improve the reliability of these devices while SSD and other subsystem manufacturers are working to develop system-level techniques to mask the reliability of these devices. That’s not a patch job. HDD vendors have spent the last 50 years paving over the data-reliability problems of rotating magnetic storage and no one pays much attention any more except the engineers tasked with keeping those problems at bay. Much the same will happen for NAND Flash devices and for products based on those devices.

NAND Flash prices firm up – NAND Flash prices have recently risen and a lack of capital investment in new fabs and processing equipment foretells the usual period of spot shortages and price peaks associated with scarcity. See MemoTrek’s extensive analysis: NAND Flash Prices: 4Q Trends & 2010 Forecast.

Joker’s wild – If we told you, then it wouldn’t be a surprise, would it?

Please have a happy and safe New Year’s celebration and we’ll see you next year.

Find those last two sentences confusing or contradictory? Here’s the explanation.

SSDs have no read/write heads or positioning arms. Instead, they consist of several NAND Flash chips and a controller chip. There’s an array of memory blocks on each NAND Flash chip. The size of the Flash memory block is the smallest amount of memory a NAND Flash chip can write in one operation because NAND Flash memory blocks are atomic with respect to erasure. You can’t write just one byte or word because you must erase the entire block before writing to the block. That means an SSD can only write an entire NAND block at a time.

Here’s a graphic from Jim Handy’s SSD keynote at the Bell Micro SSD seminar held in early December that helps to explain the situation:

Each SSD consists of a stack of visible NAND memory blocks that the SSD controller uses to store written data. There’s also a shorter stack of spare NAND memory blocks that hold data in temporary storage. These spare blocks are also used to replace a visible block when it wears out from repeated write/erase cycles. All NAND blocks are equally accessible, so there’s no time penalty for writing NAND blocks out of sequence as there is when writing on non-adjacent or non-contiguous tracks with HDD storage.

However, most virtual operating systems don’t write in blocks, they write in 4-Kbyte pages that are much smaller than NAND Flash blocks. For example, Numonyx’ 1-to-16-Gbit NAND Flash devices have 128-Kbyte blocks. As a result, modifying one 4-Kbyte page in a NAND Flash block requires a relatively complex sequence:

1. Read the data for the entire block from NAND Flash into a RAM buffer
2. Modify the appropriate page in the block image now stored in RAM
3. Write the block back to an erased NAND Flash block
4. Fix pointers to the new memory block
5. Erase the old memory block as a background task

Consequently, SSD performance varies over time and the performance varies depending on how many erased and spare memory blocks are available across all of the NAND Flash chips in the SSD. SSD performance also depends on the ratio of reads versus writes—because reads occur ten times faster than writes for SSDS—and they vary over time as the NAND Flash chips fill up.

The following figure from Handy’s keynote shows a 3D data surface plot representing the IOPS performance of one SSD. (The figure is from a presentation at the August 2009 Flash Memory Summit made by Esther Spanjer, Director of SSD Marketing at Smart Modular Technologies.)

The X axis of the surface shows the ratio of reads to writes and varies from 100% writes on the left to 100% reads on the right. The Y axis shows SSD performance in IOPS. The Z axis plots “block” size, from the SSD-level perspective (which is page size from the NAND Flash chip’s perspective, yes that’s confusing).

The first thing to note from this surface plot is that performance is a lot better on the right-hand side, which is dominated by reads. You’d expect that because SSD read performance is 10x better than SSD write performance. It’s the nature of NAND Flash memory. Note how fast the performance falls off as the percentage of write transactions increases. Then note that there’s a sort of saddle effect along the Z axis. The saddle peaks at 4-Kbyte blocks. Most SSD designs are optimized for 4-Kbyte blocks because most virtual operating systems employ 4-Kbyte blocks (and have for decades, in spite of the radical, orders-of-magnitude increase in memory use by both operating systems and application software).

So, clearly, when an SSD vendor gives an IOPS rating for an SSD, you need to take that one number with a grain of salt. SSD performance varies significantly depending on the read/write mix and on block size. Consequently, SSD performance can’t be captured in one or two numbers.

Next, Handy presented this graphic from SandForce (which makes SSD controller chips):

This graph shows an initial conditioning period during which the test preconditions (fills up) the SSD using sequential 128-Kbyte writes. The initial transfer performance (about 80 Mbytes/sec for the particular drive being tested) drops slightly as the drive fills and the internal SSD controller starts shuffling full NAND Flash blocks off to spare memory. The falloff isn’t big because the sequential writes place a predictable load on the SSD controller. However, when the test switches to random 4-Kbyte writes about 4000 seconds into the test, performance drops significantly because the SSD controller suddenly needs to make small changes to memory stored in the NAND Flash blocks but the drive’s full and there are no empty blocks. Blocks must be erased to make room for the new data and block erasure takes time. Consequently, there’s a big performance falloff as the controller starts to shuffle data around inside of the drive to make room for new data.

Perhaps more interesting is what happens when the test switches back to large sequential writes about 11,000 seconds into the test. Initially, the sequential writes cause the drive performance to vary wildly because the preceding random writes have scattered the spare blocks and left them distributed throughout the SSD’s internal NAND Flash memory space. Eventually, the SSD’s internal controller gets things sorted out and the performance for large sequential writes returns to the initial steady-state level.

(Note: This graph is not supposed to typify the performance of all SSDs. The graph shows the results of a test on one particular SSD.)

So what’s to be learned from all of this data? SSD performance measurement isn’t simple. Creating controllers and firmware that deliver optimum SSD performance isn’t simple either. As drive and chip vendors learn more about the use of NAND Flash for storage, they develop better algorithms for extracting more performance from the NAND Flash chips.

NAND Flash chips are complicated, whether used in SSDs or for server memory backup as with AgigA Tech’s AGIGARAM modules. It takes experience to get the most performance from these memory devices.

My thanks to Jim Handy for all of the great information in his Bell Micro keynote, and for generously letting me use the information in this series of blog entries.

First, take a look at this graphic depicting a “typical” server storage array consisting of 100 enterprise-class HDDs.

Each short-stroked, enterprise-class HDD has a capacity of 300 Gbytes, for a total array capacity of 30 Tbytes. This enterprise-class HDD array delivers 30K IOPS, costs $55,000, and consumes 1.75 kilowatts of electricity (not to mention an equivalent amount of electricity required for cooling). That’s the baseline.

Now look at this graphic, which compares the previously discussed array of enterprise-class HDDs with a hybrid array consisting of one SSD and 30 high-capacity, 1-Tbyte HDDs.

The high-capacity drives are not short-stroked, so they can provide a total storage capacity of 30T bytes with only 30 drives instead of 100 enterprise-class HDDs. However, the one SSD inserted into the drive array provides the same IOPS read performance as the 100 enterprise-class HDDs, so the use of the slower, less expensive, high-capacity HDDs in the second array is not a detriment to the second array’s IOPS performance, as long as the server software is written to make use of the hybrid array’s abilities.

The SSD-enhanced drive array costs $6040 or about 90% less than the array of 100 enterprise-class HDDs. The SSD-enhanced array consumes 0.392 kilowatts, which is nearly 80% less than the enterprise-class array of 100 short-stroked HDDs. Consequently, the second drive array generates substantially less waste heat (that must be cooled) than the full array of enterprise-class HDDs.

As a result, the SSD-enhanced drive array saves the enterprise customer a substantial amount of money when viewed from a systemic perspective. Relative to the enterprise-class HDD array, the SSD-enhanced hybrid drive array costs less to purchase; costs less to provision because fewer drives require less rack space and fewer racks; consume less electricity for operation; need less electricity for cooling because fewer, slower drives generate less heat; and reduce maintenance costs because the high-capacity drives run cooler (increasing MTBF), because there are fewer drives to maintain, and because high-capacity drives are much less expensive than enterprise-class drives. Overall, the TCO calculations favor the SSD-enhanced, hybrid drive array.

Handy took Sun’s numbers a step further by calculating the crossover point where TCO considerations favor an SSD-enhanced drive array over an array of enterprise-class HDDs when the IOPS performance is the main consideration rather than capacity. Here are Handy’s graphs:

The left graph shows price curves for an array of enterprise-class HDDs versus an array of SSDs. The array of SSDs initially costs more than the enterprise-class HDDs, so the crossover point is 1200 IOPS due to the high initial SSD cost. As the IOPS requirement rises, you need to add enterprise-class HDDs to the array to meet the higher IOPS requirements but one SSD gets you a lot of IOPS so there’s no need to add one until the IOPS requirement exceeds around 3000 IOPS. For the enterprise-class hybrid array, which mates one SSD with several high-capacity HDDs, the purchase cost of the SSD-enhanced array is much lower for a given capacity so the crossover point is also lower—just 400 IOPS.

TCO computations such as these are required for storage and for memory subsystems. It’s easy to be myopic and compare component cost to component cost, but system architects are creating systems and should always try to view component costs through a TCO lens.

For this blog entry, we’re returning to the Flash Zone, a concept described by Denali Software’s CTO Mark Gogolewski in his keynote speech—The World is Flash: A Disruption of the Memory & Storage Hierarchy—at Memcon 2009. The Flash Zone is the name put to the performance gap between DRAM and disk storage. There’s not only a gap in performance within the Flash Zone, there’s a transition from volatile memory (DRAM) to non-volatile storage (hard disk). With steep cost/bit price declines and per-device capacity growth, NAND Flash devices now easily fit into this gap and produce a new and viable layer in the overall computer memory hierarchy.

What’s new is that Jim Handy’s keynote at the Bell Micro SSD seminar put some welcome numbers on the Flash Zone that further clarify Flash’s place in the hierarchy. Here’s an image of that particular slide.

This image plots the performance and cost of the different memory hierarchy layers from first-, second-, and third-level processor cache through DRAM, disk, and tape. Because Handy’s used a log-log scale to plot everything, the graph looks nice and linear even though the reality is quite a bit messier. For a conceptual graph however, this’ll do nicely.

Note that there’s a gap in the hierarchy. That’s the Flash Zone. Here’s the same plot augmented a bit. The big red circle identifies the Flash Zone.

Also note that Handy has labeled the gap and says it’s “growing.” The gap’s growing because DRAM is getting faster, bigger, and cheaper, moving its ellipse up and to the left while HDDs are getting bigger, although not much faster, moving the HDD ellipse horizontally to the left. The result is a growing performance and bandwidth gap between DRAM and HDDs.

Flash fits into this gap very, very nicely said Handy (and as discussed in this blog previously). Later in his keynote, he displayed this image to underscore the point.

There are currently at least three ways to fill the Flash Zone in a memory hierarchy using NAND Flash memory. The first way, the way that gets the most attention these days, is with solid-state drives (SSDs). Because they employ the same interfaces and share the same form factor with HDDs, SSDs are an easy, drop-in Flash Zone filler. They boost performance just by dropping them into place as HDD replacements, although that may not be the best way to introduce SSDs into the hierarchy. (More about that in a later blog.)

The second way to drop NAND Flash memory into the Flash Zone is through direct- or I/O-attached drives. This is the approach advocated by Fusion-io, as discussed in that earlier AgigA Tech blog entry on the Flash Zone. Direct-attached SSDs eliminate the HDD interface and protocols, which were designed with built-in assumptions about the performance characteristics and limitations of HDDs (“rotating rust” quipped Scott Stetzer, VP of Marketing at SSD vendor STEC). Free of those limiting assumptions and limits, direct-attached SSDs deliver more performance than do SSDs employing HDD interfaces.

Handy showed the ways to introduce these two types of SSDs with the following slide:

In enterprise-class server systems, SSDs with HDD interfaces typically plug into SAN racks and tie to servers over a network while direct-attached SSDs plug directly into the server over a high-speed interface (typically PCIe). Note that smaller servers with HDD interfaces often talk to SSDs directly.

Because he was speaking at an SSD seminar, Handy did not discuss the third way of introducing NAND Flash into the Flash Zone—the approach employed by AgigA Tech’s AGIGARAM. That approach mates the NAND Flash directly to the server’s DRAM, creating a high-bandwidth connection between the two memory hierarchies. In this application, however, the NAND Flash is used for DRAM backup and power-failure bulletproofing—not necessarily for storage (although there are other possibilities to be discussed in this respect).

So far, we’ve only been able to discuss two of Handy’s 47 keynote slides. The talk contained a ton of good information for server designers and enterprise system architects. More later.

Note: Handy’s keynote was based on his company’s new report: Solid State Drives in the Enterprise – 2010.

With IC lithographies approaching atomic limits—and our absolute inability to pattern transistors using fractional atoms that inevitably leads to the subsequent slowing of Moore’s-Law scaling—a third dimension starts looking mighty attractive. Just as cities started to build up towards the sky to fit more people and more businesses into limited downtown real estate, IC designers would dearly love to find easy ways to pack more transistors, more gates, and more bits into the same limited on-die real estate. One way to do this is to build circuits in layers. Intel and Numonyx will be discussing a new way to build nonvolatile phase-change memory (PCM) ICs using multiple layers in a few days at the IEDM conference in Baltimore, Maryland. But NAND Flash designers have already discovered another way to pack more bits into the same space by stuffing existing 2D memory cells with multiple bits. This approach also represents a way to circumvent 2D limits—to put NAND Flash bit capacity on a trajectory that is “more than Moore.”

Flash memory stores bits as charge trapped in a transistor’s floating gate, which is an isolated island of semiconductor surrounded by insulator. Electron tunneling drives the charge into the floating gate through where it *mostly* remains trapped until erased. (Sometimes, the electrons wander off by themselves or through a phenomenon called “read disturb.”) The electrons trapped in the floating FET gate act like a phantom negative voltage that prevents the transistor from conducting when read. This is the original mechanism developed for the NAND Flash memory by Dr. Fujio Masuoka while working for Toshiba circa 1980. It’s a simple binary use of trapped charge. When charge is trapped in the NAND Flash cell’s floating gate, the associated transistor will not conduct when read. When there are no trapped electrons, the transistor will conduct during a read operation. You get a simple binary response to the trapped charge or lack of trapped charge.

However, there’s an essential analog mechanism available here. The Flash memory can trap more or fewer electrons in the floating gate. The variable amount of charge can be measured by a fast A/D converter. If you store four different charge amounts on a floating gate (empty, quarter full, half full, three quarters full, and full) then you have essentially put two bits (four states) worth of information in one NAND Flash memory cell. If you can trap and measure eight charge levels of charge in a NAND Flash memory cell, then you have essentially put three bits worth of information into one NAND Flash memory cell. NAND Flash memories that store one bit/cell are called single-level cell (SLC) memory. Store two bits/cell and you have multi-level cell (MLC) memory. Store three bits per cell and you have three-level cell (TLC) memory (or 3BPC—three-bit/cell—memory using Micron Technology’s terminology).

Great! Why not pack two or three bits worth of information into every NAND Flash memory cell and essentially boost the NAND Flash chip’s memory capacity “for free?” Well, why not?

There are a few reasons why not. First, MLC and TLC NAND Flash memory is slower than SLC NAND Flash memory. You need more time for the on-chip A/D conversion circuitry to resolve the amount of charge stored in the selected cell. Second, there are more and more complex wear, reliability, and endurance issues with MLC and TLC NAND Flash memory than for SLC NAND Flash memory. One NAND Flash wearout mechanism involves permanently trapped charge and MLC and TLC NAND Flash memories are more susceptible to such failures because the exact amount of charge trapped by the tunneling process is far more critical when storing more bits per cell. A little permanently trapped charge can really mess things up.

Choosing between SLC, MLC, and TLC memory can be tricky. The choice involves several of your design criteria including the simple and obvious one (read/write latency requirements) and the more fuzzy ones (failure rate, reliability, and cycle endurance). In short, you cannot choose using a simple cost/bit analysis.

Finally, if you’d like a painless video intro to the world of SLC, MLC, and TLC or 3BPC NAND Flash memory concepts, here’s a 5-minute video from Micron Technology:

SSDs are one of three ways to fill the memory/storage gap called the “Flash zone” as discussed in the previous AgigA Tech blog entry, which described Flynn’s initial panel presentation. Although not a major consumer of NAND Flash memory devices, yet, SSD use is growing quickly because of the speed advantages they deliver over what can be achieved with rotating mechanical storage (hard disk drives). Flynn’s talk described the ideal conditions under which I/O-attached storage (including products offered by Fusion-io) can deliver stellar storage performance as measured in IOPS. Flynn’s presentation prompted the first panel question from moderator Coughlin: “Are hard disk drives dead?”

Flynn answered first. Unsurprisingly, he said “No.” Tape hasn’t died either, said Flynn, and neither has DRAM. None of these technologies is in danger of disappearing overnight. HDDs (hard disk drives) currently enjoy a huge cost/capacity lead over any competing storage technology (excluding tape) and HDDs will only disappear when they lose that lead.

Speiser also weighed in. Tape’s huge cost/capacity lead over HDD storage is the only factor that keeps tapes alive for their ultimate use: “offline storage inside of (hollowed-out) mountains.” Tapes will outlast HDDs added Speiser. “They’re the cockroaches of the storage industry.” Chenery, who left HDD vendor Fujitsu in 2006 to start SSD supplier Pliant, also spoke favorably about HDDs. “No one wants a mechanical drive in their computer,” said Chenery, because of the power consumption and susceptibility to physical shock. However, “they provide so much value for capacity” he explained. “In 30 years, who knows?”

Watkins disagreed. “No one cares what’s in their PCs. Consumers think about the applications they want to run. Then they find the best hardware to fit their needs.” Watkins is more concerned by the applications that consumers will be using in five years. His conclusion: all mobility products will evolve into Flash-only use because Flash memory provides superior form factors for small, mobile end products. Meanwhile, cloud storage may obsolete large HDDs in laptops because it’s too dangerous to carry around all that valuable data in a form where it can be lost, stolen, damaged, or destroyed. Yahoo’s Pullara smiled at Watkins’ comment about cloud storage and quipped “How about unlimited storage (in Yahoo’s cloud)? Can you beat that, Google?”

“So if HDDs aren’t going away any time soon,” asked Coughlin, “why did you (Chenery) start Pliant?”

“Because no one would listen to me” replied Chenery, who feels that SSDs are clearly going to redefine they way computer systems are architected.

Speiser jumped on the bandwagon. “We’re looking to invest in companies that have fundamentally rethought applications to back out assumptions based on spinning media.”

Pullara concurred. “Look at anti-spam in 2003” he said. The need to maintain extensive lists of spam sources has soared since then. Maintaining those lists on slow HDDs would make it impossible to reject spam in real time, given the rising volume of spam emails.

Watkins returned the discussion to mobile applications. “The sweet spot for Flash is in the hand,” he said. SSDs must reach 100-Gbyte capacities for netbooks while enterprise applications require terabytes of data storage and corresponding changes in server architecture.

The question of data reliability and trust then arose. Flash memory has well-documented, well-understood wearout and failure mechanisms. In fact, Flash vendors have been far more open and informative about these technology issues than have HDD vendors. As a result, people better understand Flash failure modes and are more aware of them. Chenery grinned and asked “Why would you trust your data to a flying head on a disk?” referring to the incredibly small gap between the read/write head and the spinning media. Head crashes are a well-known HDD failure mechanism. “Flash memory has its idiosyncrasies, but technology overcomes a lot of these” said Chenery. “You manage these idiosyncrasies with appropriate controllers, software, and use models.” In the end said Chenery, system-level designers shouldn’t trust any of the HDD or SSD vendors. They should test and verify reliability claims.

In addition, said Chenery, SSDs don’t “fall off the cliff” (fail catastrophically like HDDs). They provide deterministic, predictable performance that allows for soft failures, usually seen as a gradual capacity decrease as control firmware walls off bad blocks in the Flash memory and moves data to good blocks. Most SSDs will decline in performance over time, claimed Chenery. They must be designed specifically to not decline in performance at the subsystem level. “Getting Flash to deliver deterministic performance in a random environment is hard. It requires enormous computing power.”

• Solid-state disk drives (SSDs). With SATA and SAS interfaces, SSDs can plug directly into most existing systems and will provide an immediate performance boost.
• Flash caches. Located very near the DRAM, Flash caches provide fast ways to back up DRAM data over wide memory buses with high bandwidth and low latency. AgigA Tech’s AGIGARAM and Denali’s FlashPoint controller are both aimed at this NAND subniche.
• Specialty storage devices based on non-disk interface standards. Disk interfaces including SATA and SAS were developed with built-in assumptions about the drives they support. Those assumptions include some temporal assumptions based on having rotating mechanical memory. Those assumptions don’t apply to NAND-based storage devices so it’s possible to use interfaces with more bandwidth, PCIe and Hypertransport for example, to connect such storage and get better performance. This is the sort of product available from Fusion-io.

Which finally brings us to the trigger for this blog entry. The MIT/Stanford Venture Lab (VLAB) held a panel discussion at Stanford University on Tuesday, November 17 and the evening’s topic was “SSDs: Game-Changing Technology for Better, Bigger, Faster Applications and Application Development” and the first speaker was David Flynn, President and CTO of Fusion-io. Flynn’s talk contained many interesting and worthwhile things for followers of NAND-related topics as they relate to computer system design.

Early in his presentation, Flynn projected a photo of Charlie Chaplin playing one of the last great roles of his life, “The Great Dictator.” However, Chaplin’s roundish face had been replaced with an inset photo of a hard-disk platter and the caption was: “Getting rid of nasty Disc-tators.” Flynn emphasized that Fusion-io’s PCIe-connected products are not solid-state disks and they deliver more performance than solid-state disks because they are connected to a data pipeline that delivers more performance than existing disk interfaces. They are I/O-memory devices that provide 10x the capacity of DRAM per dollar, 50x the capacity of DRAM per “module,” and 100x the capacity of DRAM per Watt. Using these metrics, Flynn is making it clear that he understands the figures of merit valued by his company’s prospects.

Flynn then compared NAND Flash memory to aircraft aluminum. When metallurgists developed aluminum alloys suitable for aircraft, the entire airframe had to be re-engineered because aeronautical engineers couldn’t use aluminum as a direct replacement for wooden struts and dope-covered fabric. Aluminum ushered in new types of airframes that rapidly evolved. Aircraft performance soared as a result.

The same is true of computer systems (and software) developed before and after the Flash Zone is filled with something, whether it’s SSDs, Flash caches, or I/O-attached storage. Assumptions must be rethought and systems and software need to be redesigned to fully exploit the advantages of a populated Flash Zone.

There’s a similar but even larger performance gap between the access time of DRAM and HDDs. Although vendors have improved HDD capacity by 60% per year—each and every year—and HDD’s price per storage bit directly tracks that trend as well, there’s been very little improvement in HDD data transfer rate and interface speed and there’s been no dramatic change in HDD access time, which is largely determined by mechanical factors. Consequently, there’s been only a relatively slow improvement in HDD IOPS (I/O operations per second), which leads to a massive five-orders-of-magnitude (10^5) performance gap between DRAM access times and HDD access times and that performance gap is growing.

At the same time, DRAM’s volatility plays a role in a system’s sensitivity to power glitches and losses. When data is critical, and most data is critical these days, non-volatile memory just isn’t sufficient. Some means of retaining data through a power loss is usually required. In the past, HDDs have sufficed for non-volatile storage but they’re simply too slow these days.

The Flash Zone

Flash memory is a good candidate for filling this memory gap because it provides nonvolatile storage and it has become the cost-per-bit leader in semiconductor memory. Consequently, Mark Gogolewski, Denali Software’s CTO, calls this performance gap in the memory hierarchy the “Flash Zone” (see figure below and the Reference), the performance zone between DRAM and HDD access times.

The Flash Zone in memory hierarchy

The reasons for Flash memory’s candidacy to fill this gap include:

• In 2004, the per-bit cost of NAND Flash dropped below the previous category leader, DRAM.
• More NAND Flash bits shipped in 2005 than bits of any other type of semiconductor memory.
• More NAND Flash bits shipped in 2007 alone than all of the DRAM bits shipped in the last 25 years of commercial DRAM production.

There’s been a huge decrease in the per-bit cost of NAND Flash and a big capacity increase on a NAND Flash die. Consequently, NAND Flash memory fits nicely in the gap between DRAM and HDD. It offers faster access speeds than HDDs by at least two orders of magnitude while replicating an HDD’s non-volatile storage abilities. In addition, NAND Flash memory can draw considerably less power than HDDs when managed correctly. The opportunity for innovation in memory hierarchy is therefore huge.

Three Ways to Use NAND Flash: SSDs, Flash Cache, DRAM Backup

There are three ways to fill the Flash zone. The first approach is to use NAND Flash memory to create an HDD emulator using the same disk interface and possibly even the same form factor. Such drives are called solid-state drives (SSDs) and they have been gaining traction in the industry. Because they do not employ rotating memory, SSDs can deliver far faster access times than HDDs. However, there are costs associated with this approach. SSDs cost substantially more per stored bit than HDDs while retaining the overhead associated with HDD interfaces and protocols. The memory bus protocols and interfaces used to connect DRAMs to processors are much, much faster.

At this time, most analysts agree that NAND Flash memory will not overtake HDDs in cost per bit. Jim Handy of Objective Design presented the chart shown below at MemCon 2008 showing that the 25x cost-per-bit advantage for HDDs relative to NAND Flash memory cost per bit would continue for the foreseeable future.

NAND Flash and HDD cost-per-bit forecasts
(Jim Handy, Objective Design)

Denali’s memory market analyst Lane Mason recently commented that the pace of cost-per-bit reductions for NAND Flash memory will actually slow compared to price drops in recent years. So it doesn’t appear that NAND Flash will supplant HDD storage in the near- or medium-term future.

The second way to use NAND Flash memory in the Flash Zone is called a Flash cache. A Flash cache speeds access to an HDD by buffering the data stream between a processor and the HDD. Data is drawn from and written to HDDs as needed and the same data is simultaneously cached in NAND Flash. The next time this data is needed, it’s drawn directly from the Flash cache instead of the slower HDD. Flash caches do not require as much NAND Flash memory as SSDs, and therefore cost less, but they can deliver performance improvements when paired with HDDs.

The third way to use NAND Flash memory is to implement a backup strategy that allows the DRAM to operate normally when system power is available and to quickly save that data in non-volatile NAND Flash when system power fails. In this approach, which is used in AgigA Tech’s AGIGARAM Non Volatile System (NVS) modules, a backup power source provides the energy needed to safely tuck data away in non-volatile storage (NAND Flash), which then retains the data for a decade or more if needed.

This third approach to filling the Flash Zone offers several benefits including:

1. Fast backup when power fails
2. No energy required to save the data during power failure
3. Automated backup and restoration of data with no host-based software assist required

Which of these three approaches to use depends on the application (as always). If you’d like help deciding, please feel free to contact AgigA Tech.

Reference

The World is Flash: A Disruption of the Memory & Storage Hierarchy, Keynote Speech, Denali Memcon 09, Mark Gogolewski, CTO, Denali Software, Inc., www.denali.com