Here’s the testbed that Gavrichenkov used for his tests:

• CPU: Intel Core i7-860 (Lynnfield, 2.80 GHz, 4 x 256 KBL2, 8 MB L3)
• Mainboard: ASUS P7P55D Premium (LGA1156, Intel P55 Express)
• System memory: 2 x 2 GB, DDR3-1600 SDRAM (Kingston HyperX KHX1600C8D3K2/4GX, Corsair Dominator CMD4GX3M2A1600C8)
• Graphics card: ATI Radeon HD 5870
• HDD: Western Digital  VelociRaptor WD3000HLFS
• PSU: Tagan TG880-U33II (880 W)
• OS: Microsoft Windows 7 Ultimate x64

Using memory-intensive synthetic benchmarks, Gavrichenkov did observe some performance differences between DDR3-1067 and DDR3-1600 SDRAM. Although the DDR3-1067 clock and transfer rates are 37% slower than for DDR3-1600, Gavrichenkov observed a maximum of 18% performance difference between the two DDR3 SDRAM speed grades. Results from a multi-threaded synthetic benchmark called MaxMEM2 showed that DDR3-1600 SDRAM gave a maximum of 40% more performance than DDR3-1067 SDRAM, suggesting that multithreaded processor operations get more benefit from faster SDRAM transfer rates. Published results for non-synthetic video-transcoding, X.264 video-decoding, and file-compression benchmarks seem to verify the synthetic benchmark results, at least qualitatively. The Intel Core i7 processor does get some benefit from the faster SDRAM in the benchmarks based on real-world applications.

To some extent, these results should not surprise anyone familiar with the Intel Core i7 multicore processor architecture. The chip carries four multithreaded processors cores. Each processor core has private L1 and L2 caches and all four cores share a large, 8-Mbyte, 16-way associative L3 cache called the “last-level cache” or LLC. There are three SDRAM channels run by an on-chip Integrated Memory Controller (IMC), which manages the traffic between the LLC and the attached SDRAM.

The LLC serves as a huge buffer between the Core i7 processor’s multiple processor cores and the SDRAM channels and it makes sense that the LLC can damp down the performance differences among DDR3 SDRAM speed grades for single-threaded environments. That’s what a good cache does. It also makes sense that the buffering job gets harder when multithreading is involved because the memory accesses become less correlated and therefore too messy to cleanly cache.

Do the Xbit Labs’ results hold true in a server environment? Good question. The results suggest that server designers ought to be running tests of their own. At least for servers based on the Nehalem architecture (Intel’s Core i7, Core i5, Core i3, and Xeon processors), that big on-chip LLC could represent significant savings with respect to memory costs.

The reason behind the rising DRAM chip and module pricing was predictable by anyone who has followed the semiconductor industry for a decade or two. The last few years have been rocky for semiconductor memory vendors and whenever times are tough, these vendors know what to do to drive prices up: reduce capital expenditures, stop building memory fabs, and stop making so many memory chips. And that’s exactly what’s happened. It helps that in tight economic times, it’s relatively easy to forego the big capital expenditures needed to build new memory fabs or refit older fabs with new chip-making equipment.

DRAM Exchange provided a little fire to burn that coal in your stocking with the following heat-up-the-market predictions:

1. Capital expenditures for DRAM vendors will increase 80% year over year to US$7.85B from US$4.30B in 2009
2. DRAM aggregate demand will be slightly below aggregate supply in Q1 2010
3. DRAM pricing will fall appropriately 10% to 20% quarter over quarter in Q1 2010

DRAM Exchange also made the following predictions for DDR3 DRAM in the coming year:

1. DDR3 DRAM goes mainstream in Q1 2010
2. DDR3 DRAM market share will account for 60% and will likely reach 80% of commodity DRAM by 2H 2010
3. DDR3 DRAM prices will decline less than DDR2 DRAM prices given the strong platform migration momentum

Like Dickens’ ghosts of Christmas past, present, and future in “A Christmas Carol,” (go see the new movie!), these predictions from DRAM Exchange are merely shadows. Reality may or may not prove the predictions correct. Make your own decisions. TG Daily picked up DRAM Exchange’s predictions of a DRAM shortage for 2010 and one reader commented: “Prfft, they said the same thing last year.”

• More density
• More speed
• Less cost
• Less power

Depending on the specific application, one or two of these major factors may be more important than the other, but they’re all important factors—all of the time.

Currently, we have divided the use space for semiconductor memory into four big regions:

• SRAM serves applications that require frequent, fast data access—more speed (usually cache)
• DRAM serves applications that need large storage space—more density—for frequently changing data at a low price—less cost
• NOR Flash currently serves the spot for holding code and data that must be accessed quickly—more speed—but doesn’t change often. You see NOR Flash mostly in smaller embedded applications because larger embedded applications, computers, and servers combine hard disk drives (HDDs) or solid-state disks (SSDs) with DRAM to serve the same function instead of NOR Flash.
• NAND Flash is a story all by itself. As an industry, we use NAND Flash in a wide variety of ways. We use it to hold data and code in bulk because it’s the cheapest semiconductor memory available—less cost. At the same time, NAND Flash is non-volatile, so it’s useful for retaining information through power outages. That’s why SSDs are packed with NAND Flash chips and it’s also why AgigA Tech uses NAND Flash to back up DRAM in its AGIGARAM bulletproof Non Volatile System (NVS) memory modules. Even better, NAND Flash power consumption is fairly low—less power—if the system uses the NAND Flash memories infrequently, which is exactly how they’re applied in AGIGARAM NVS memory modules.

Memory Technology Inflection Points

The immense importance of memory in a processor-centric, multicore world results in tremendous technology R&D efforts to develop semiconductor memories that improve on one or more of the four major factors listed above. Memory storage technology and memory cell design get a lot of attention. One aspect of memory design that sporadically pops up in importance is the memory interface.

For some, the memory interface isn’t nearly as glamorous as a new kind of memory cell (think phase-change memory or PCM, which has held the limelight lately) or lithographic shrinks (think 32nm heading for 2x nm). However, the memory’s interface performance plays a major role in determining how a memory performs and even how much power it consumes.

In the world of NAND Flash, ONFi (the Open NAND Flash interface) and the Toggle-Mode NAND interface are coming to the fore. We’ll leave the discussion of these competing, high-speed NAND Flash interfaces for another blog post. Today’s topic is DRAMs. For DRAMs, the hot “new” interface is DDR3, which is the third major iteration of the JEDEC interface standard for synchronous, double-date-rate (DDR) DRAM.

The original DDR (double data rate) specification appeared in June, 2000 after a four-year gestation. The DDR memory interface replaced the original JEDEC SDRAM interface, which appeared in 1993. Before that, DRAM used the baroque RAS/CAS asynchronous control structure and multiplexed row/column address lines that Mostek developed for the MK4096 4-kbit DRAM in 1973 to reduce package pin count. That old RAS/CAS stuff is still there, deep inside of today’s advanced DRAMs, but it’s now buried inside of the DDR parts where you can’t see it unless you’re a DRAM chip designer.

DDR3 Memory’s Advantages

What are the advantages of DDR3 over DDR2? They go straight back to the four major factors listed at the beginning of this blog post. Compared to DDR2, DDR3 memory provides more speed, more density, operates at lower voltage (and therefore consumes less power), and it will be less expensive than DDR2 memory at some point in the coming year. In short, DDR3 memory improves on all four of the major factors relative to DDR2 memory. Bets don’t get much safer than that.

For enterprise-class systems (servers), DDR3 memory provides many specific advantages. First, it promises denser memory modules by accommodating DRAM chips as large as 16 Gbits, permitting the development of 16-Gbyte registered DIMMs. Enterprise-class server architects love denser memory modules because they’re always strapped for room inside of their server boxes. DIMMs take up space and, worse, they block air flow and make cooling more difficult inside of the enclosures. Fewer DIMMs is definitely better for air flow.

Second, DDR3 memory transfers twice as much data per clock as DDR2 memory. Enterprise-class server architects can use this speed in one of two ways. They can run their processors faster with faster memory or they can run at the same speed but cut the clock rate to the memory modules and thus cut power consumption.

Real Power Savings

But the real power savings comes from DDR3’s lower operating voltage. DDR2 memory is specified for a 1.8V operating voltage while DDR3 memory operates at 1.35V (and maybe 1.2V in future low-power DDR3L devices). Because operating power is proportional to the square of the operating voltage, that small 150mV drop between DDR2 and DDR3 operating voltages translates into an appreciable drop in operating power—about 30% less!

Enterprise-class server designers like lower operating power, therefore less waste heat. In fact, they like it a lot. That’s because data centers pay double for every excess Watt of server power. Roughly speaking, each Watt consumed by a server takes one Watt of electricity to run and another Watt to cool the server. By at least one estimate, DRAM power usage accounts for 25% to 40% of a data center’s energy costs (and can be more than 50% according to this Denali memory blog post). By another estimate, Google’s power costs were $50 million in 2006. So power reduction is very high on the server designers’ wish lists because data-center operators can easily translate reduced power consumption into monetary savings and they are quite aware of that sort of calculation with respect to total cost of ownership (TCO) when evaluating competing servers.

Perhaps the biggest force driving the adoption of DDR3 memory is the support of Intel and AMD. Intel’s Core i7 and AMD’s Phenom II multicore processors and chipsets presume DDR3 memory. It won’t take long before this presumption filters down to the lesser PC processors and PC processors are the big dogs in the memory kennel. They largely drive what happens with mainstream DRAM parts. So DDR3 memory’s success is likely assured, just as DDR2’s was before that and just as DDR memory supplanted SDRAM. The cycle repeats, and often.

Currently, AgigA Tech offers AGIGARAM NVS modules with SDRAM and DDR2 interfaces. It doesn’t yet offer an off-the-shelf DDR3 module, but given the industry’s track, you can safely bet that there’s a DDR3 AGIGARAM module on the road map.