2x nm will happen – Currently, vendors are shipping 34nm NAND Flash memory in volume. That’s a tremendous engineering feat in itself. As reported in an earlier blog entry (“Intel, Micron striving to regain lead in NAND tech”), Intel and Micron Technology are apparently planning to ship NAND Flash devices based on 2x nm lithography (called 2x because it’s not yet clear if it’s 26nm, 25nm, 24nm, or 22nm). Lithography shrinks are a true race to the bottom. Features on chips have become so small that one or two atoms of difference from one part of a chip to another cause real changes in device characteristics. This phenomenon is called on-chip variation or on-chip variability (OCV) and it’s a tough problem to tackle, requiring the use of smarter on-chip circuitry to deal with the variation. (See “My Head Hurts, My Timing Stinks, and I Don’t Love On-Chip Variation” by Matt Weber.) The problems do not appear to be insurmountable and NAND Flash vendors currently leading the lithography derby appear intent on keeping that lead until it’s no longer possible.

SDDs will get bigger and faster – This prediction needs to be written, but it’s really a no-brainer. The “bigger” part of the prediction is based on the ever-increasing capacity of the NAND Flash chips used to make SSDs. They will get bigger, driven by economic forces far beyond SSD usage. USB Flash-memory drives are the big volume driver in this market and there’s always demand for more capacity there while the form factor emphasizes small and slim. Nowhere to go but more on-chip capacity. Number two driver is SD cards for cameras and camcorders, with the same forces at work. As for faster, it’s clear that SATA 6G is in the immediate future for SSDs. Marvel’s SATA 6G controller (see “Early Results Show SATA 6G Performance All Over the Map”) and Micron’s introduction this month of an SSD that exploits SATA 6G to good effect (see “New SSD Introductions from Seagate and Micron”) clearly point the way to faster SSD operation, once the internal architectural designs are aligned with the faster interface.

ONFi 2.1 gets big – ONFi stands for the “Open NAND Flash interface” and the ONFi organization (www.onfi.org) bills it as the fastest Flash interface on the planet. Hyperbole aside, ONFi supports transfer rates to 200 Mbytes/sec. and that’s speedy in anyone’s book. The ONFi Working Group was formed in May 2006 and currently has over 80 member companies including Hynix Semiconductor, Intel Corporation, Micron Technology, Inc., Numonyx, Phison Electronics Corporation, Sony Corporation and Spansion. Wanna fight those guys as a group?

MLC and TLC get big – It’s already happening. Several NAND Flash vendors already offer MLC (multi-level cell) and TLC (three-level cell) NAND Flash devices. They are working to improve the reliability of these devices while SSD and other subsystem manufacturers are working to develop system-level techniques to mask the reliability of these devices. That’s not a patch job. HDD vendors have spent the last 50 years paving over the data-reliability problems of rotating magnetic storage and no one pays much attention any more except the engineers tasked with keeping those problems at bay. Much the same will happen for NAND Flash devices and for products based on those devices.

NAND Flash prices firm up – NAND Flash prices have recently risen and a lack of capital investment in new fabs and processing equipment foretells the usual period of spot shortages and price peaks associated with scarcity. See MemoTrek’s extensive analysis: NAND Flash Prices: 4Q Trends & 2010 Forecast.

Joker’s wild – If we told you, then it wouldn’t be a surprise, would it?

Please have a happy and safe New Year’s celebration and we’ll see you next year.

Here’s the testbed that Gavrichenkov used for his tests:

• CPU: Intel Core i7-860 (Lynnfield, 2.80 GHz, 4 x 256 KBL2, 8 MB L3)
• Mainboard: ASUS P7P55D Premium (LGA1156, Intel P55 Express)
• System memory: 2 x 2 GB, DDR3-1600 SDRAM (Kingston HyperX KHX1600C8D3K2/4GX, Corsair Dominator CMD4GX3M2A1600C8)
• Graphics card: ATI Radeon HD 5870
• HDD: Western Digital  VelociRaptor WD3000HLFS
• PSU: Tagan TG880-U33II (880 W)
• OS: Microsoft Windows 7 Ultimate x64

Using memory-intensive synthetic benchmarks, Gavrichenkov did observe some performance differences between DDR3-1067 and DDR3-1600 SDRAM. Although the DDR3-1067 clock and transfer rates are 37% slower than for DDR3-1600, Gavrichenkov observed a maximum of 18% performance difference between the two DDR3 SDRAM speed grades. Results from a multi-threaded synthetic benchmark called MaxMEM2 showed that DDR3-1600 SDRAM gave a maximum of 40% more performance than DDR3-1067 SDRAM, suggesting that multithreaded processor operations get more benefit from faster SDRAM transfer rates. Published results for non-synthetic video-transcoding, X.264 video-decoding, and file-compression benchmarks seem to verify the synthetic benchmark results, at least qualitatively. The Intel Core i7 processor does get some benefit from the faster SDRAM in the benchmarks based on real-world applications.

To some extent, these results should not surprise anyone familiar with the Intel Core i7 multicore processor architecture. The chip carries four multithreaded processors cores. Each processor core has private L1 and L2 caches and all four cores share a large, 8-Mbyte, 16-way associative L3 cache called the “last-level cache” or LLC. There are three SDRAM channels run by an on-chip Integrated Memory Controller (IMC), which manages the traffic between the LLC and the attached SDRAM.

The LLC serves as a huge buffer between the Core i7 processor’s multiple processor cores and the SDRAM channels and it makes sense that the LLC can damp down the performance differences among DDR3 SDRAM speed grades for single-threaded environments. That’s what a good cache does. It also makes sense that the buffering job gets harder when multithreading is involved because the memory accesses become less correlated and therefore too messy to cleanly cache.

Do the Xbit Labs’ results hold true in a server environment? Good question. The results suggest that server designers ought to be running tests of their own. At least for servers based on the Nehalem architecture (Intel’s Core i7, Core i5, Core i3, and Xeon processors), that big on-chip LLC could represent significant savings with respect to memory costs.

Both Intel and Micron are selling solid-state drives (SSDs) based on their most advanced Flash parts and so both companies have internal incentives to cut per-bit Flash costs as quickly as they can both to make their NAND Flash ICs competitive and to drive down the cost of their SSDs. Cost is now the biggest obstacle for SSDs in their quest to become mainstream storage devices.

Also according to this article, Micron Technology posted its first profit in 3 years during the period ending December 3, 2009 with sales worth $1.74 billion. The company’s NAND business rose 21% quarter over quarter and its DRAM business rose by as much as 50% during the same period. Good tidings indeed for Micron and the Flash business.

The reason behind the rising DRAM chip and module pricing was predictable by anyone who has followed the semiconductor industry for a decade or two. The last few years have been rocky for semiconductor memory vendors and whenever times are tough, these vendors know what to do to drive prices up: reduce capital expenditures, stop building memory fabs, and stop making so many memory chips. And that’s exactly what’s happened. It helps that in tight economic times, it’s relatively easy to forego the big capital expenditures needed to build new memory fabs or refit older fabs with new chip-making equipment.

DRAM Exchange provided a little fire to burn that coal in your stocking with the following heat-up-the-market predictions:

1. Capital expenditures for DRAM vendors will increase 80% year over year to US$7.85B from US$4.30B in 2009
2. DRAM aggregate demand will be slightly below aggregate supply in Q1 2010
3. DRAM pricing will fall appropriately 10% to 20% quarter over quarter in Q1 2010

DRAM Exchange also made the following predictions for DDR3 DRAM in the coming year:

1. DDR3 DRAM goes mainstream in Q1 2010
2. DDR3 DRAM market share will account for 60% and will likely reach 80% of commodity DRAM by 2H 2010
3. DDR3 DRAM prices will decline less than DDR2 DRAM prices given the strong platform migration momentum

Like Dickens’ ghosts of Christmas past, present, and future in “A Christmas Carol,” (go see the new movie!), these predictions from DRAM Exchange are merely shadows. Reality may or may not prove the predictions correct. Make your own decisions. TG Daily picked up DRAM Exchange’s predictions of a DRAM shortage for 2010 and one reader commented: “Prfft, they said the same thing last year.”

• More density
• More speed
• Less cost
• Less power

Depending on the specific application, one or two of these major factors may be more important than the other, but they’re all important factors—all of the time.

Currently, we have divided the use space for semiconductor memory into four big regions:

• SRAM serves applications that require frequent, fast data access—more speed (usually cache)
• DRAM serves applications that need large storage space—more density—for frequently changing data at a low price—less cost
• NOR Flash currently serves the spot for holding code and data that must be accessed quickly—more speed—but doesn’t change often. You see NOR Flash mostly in smaller embedded applications because larger embedded applications, computers, and servers combine hard disk drives (HDDs) or solid-state disks (SSDs) with DRAM to serve the same function instead of NOR Flash.
• NAND Flash is a story all by itself. As an industry, we use NAND Flash in a wide variety of ways. We use it to hold data and code in bulk because it’s the cheapest semiconductor memory available—less cost. At the same time, NAND Flash is non-volatile, so it’s useful for retaining information through power outages. That’s why SSDs are packed with NAND Flash chips and it’s also why AgigA Tech uses NAND Flash to back up DRAM in its AGIGARAM bulletproof Non Volatile System (NVS) memory modules. Even better, NAND Flash power consumption is fairly low—less power—if the system uses the NAND Flash memories infrequently, which is exactly how they’re applied in AGIGARAM NVS memory modules.

Memory Technology Inflection Points

The immense importance of memory in a processor-centric, multicore world results in tremendous technology R&D efforts to develop semiconductor memories that improve on one or more of the four major factors listed above. Memory storage technology and memory cell design get a lot of attention. One aspect of memory design that sporadically pops up in importance is the memory interface.

For some, the memory interface isn’t nearly as glamorous as a new kind of memory cell (think phase-change memory or PCM, which has held the limelight lately) or lithographic shrinks (think 32nm heading for 2x nm). However, the memory’s interface performance plays a major role in determining how a memory performs and even how much power it consumes.

In the world of NAND Flash, ONFi (the Open NAND Flash interface) and the Toggle-Mode NAND interface are coming to the fore. We’ll leave the discussion of these competing, high-speed NAND Flash interfaces for another blog post. Today’s topic is DRAMs. For DRAMs, the hot “new” interface is DDR3, which is the third major iteration of the JEDEC interface standard for synchronous, double-date-rate (DDR) DRAM.

The original DDR (double data rate) specification appeared in June, 2000 after a four-year gestation. The DDR memory interface replaced the original JEDEC SDRAM interface, which appeared in 1993. Before that, DRAM used the baroque RAS/CAS asynchronous control structure and multiplexed row/column address lines that Mostek developed for the MK4096 4-kbit DRAM in 1973 to reduce package pin count. That old RAS/CAS stuff is still there, deep inside of today’s advanced DRAMs, but it’s now buried inside of the DDR parts where you can’t see it unless you’re a DRAM chip designer.

DDR3 Memory’s Advantages

What are the advantages of DDR3 over DDR2? They go straight back to the four major factors listed at the beginning of this blog post. Compared to DDR2, DDR3 memory provides more speed, more density, operates at lower voltage (and therefore consumes less power), and it will be less expensive than DDR2 memory at some point in the coming year. In short, DDR3 memory improves on all four of the major factors relative to DDR2 memory. Bets don’t get much safer than that.

For enterprise-class systems (servers), DDR3 memory provides many specific advantages. First, it promises denser memory modules by accommodating DRAM chips as large as 16 Gbits, permitting the development of 16-Gbyte registered DIMMs. Enterprise-class server architects love denser memory modules because they’re always strapped for room inside of their server boxes. DIMMs take up space and, worse, they block air flow and make cooling more difficult inside of the enclosures. Fewer DIMMs is definitely better for air flow.

Second, DDR3 memory transfers twice as much data per clock as DDR2 memory. Enterprise-class server architects can use this speed in one of two ways. They can run their processors faster with faster memory or they can run at the same speed but cut the clock rate to the memory modules and thus cut power consumption.

Real Power Savings

But the real power savings comes from DDR3’s lower operating voltage. DDR2 memory is specified for a 1.8V operating voltage while DDR3 memory operates at 1.35V (and maybe 1.2V in future low-power DDR3L devices). Because operating power is proportional to the square of the operating voltage, that small 150mV drop between DDR2 and DDR3 operating voltages translates into an appreciable drop in operating power—about 30% less!

Enterprise-class server designers like lower operating power, therefore less waste heat. In fact, they like it a lot. That’s because data centers pay double for every excess Watt of server power. Roughly speaking, each Watt consumed by a server takes one Watt of electricity to run and another Watt to cool the server. By at least one estimate, DRAM power usage accounts for 25% to 40% of a data center’s energy costs (and can be more than 50% according to this Denali memory blog post). By another estimate, Google’s power costs were $50 million in 2006. So power reduction is very high on the server designers’ wish lists because data-center operators can easily translate reduced power consumption into monetary savings and they are quite aware of that sort of calculation with respect to total cost of ownership (TCO) when evaluating competing servers.

Perhaps the biggest force driving the adoption of DDR3 memory is the support of Intel and AMD. Intel’s Core i7 and AMD’s Phenom II multicore processors and chipsets presume DDR3 memory. It won’t take long before this presumption filters down to the lesser PC processors and PC processors are the big dogs in the memory kennel. They largely drive what happens with mainstream DRAM parts. So DDR3 memory’s success is likely assured, just as DDR2’s was before that and just as DDR memory supplanted SDRAM. The cycle repeats, and often.

Currently, AgigA Tech offers AGIGARAM NVS modules with SDRAM and DDR2 interfaces. It doesn’t yet offer an off-the-shelf DDR3 module, but given the industry’s track, you can safely bet that there’s a DDR3 AGIGARAM module on the road map.

Find those last two sentences confusing or contradictory? Here’s the explanation.

SSDs have no read/write heads or positioning arms. Instead, they consist of several NAND Flash chips and a controller chip. There’s an array of memory blocks on each NAND Flash chip. The size of the Flash memory block is the smallest amount of memory a NAND Flash chip can write in one operation because NAND Flash memory blocks are atomic with respect to erasure. You can’t write just one byte or word because you must erase the entire block before writing to the block. That means an SSD can only write an entire NAND block at a time.

Here’s a graphic from Jim Handy’s SSD keynote at the Bell Micro SSD seminar held in early December that helps to explain the situation:

Each SSD consists of a stack of visible NAND memory blocks that the SSD controller uses to store written data. There’s also a shorter stack of spare NAND memory blocks that hold data in temporary storage. These spare blocks are also used to replace a visible block when it wears out from repeated write/erase cycles. All NAND blocks are equally accessible, so there’s no time penalty for writing NAND blocks out of sequence as there is when writing on non-adjacent or non-contiguous tracks with HDD storage.

However, most virtual operating systems don’t write in blocks, they write in 4-Kbyte pages that are much smaller than NAND Flash blocks. For example, Numonyx’ 1-to-16-Gbit NAND Flash devices have 128-Kbyte blocks. As a result, modifying one 4-Kbyte page in a NAND Flash block requires a relatively complex sequence:

1. Read the data for the entire block from NAND Flash into a RAM buffer
2. Modify the appropriate page in the block image now stored in RAM
3. Write the block back to an erased NAND Flash block
4. Fix pointers to the new memory block
5. Erase the old memory block as a background task

Consequently, SSD performance varies over time and the performance varies depending on how many erased and spare memory blocks are available across all of the NAND Flash chips in the SSD. SSD performance also depends on the ratio of reads versus writes—because reads occur ten times faster than writes for SSDS—and they vary over time as the NAND Flash chips fill up.

The following figure from Handy’s keynote shows a 3D data surface plot representing the IOPS performance of one SSD. (The figure is from a presentation at the August 2009 Flash Memory Summit made by Esther Spanjer, Director of SSD Marketing at Smart Modular Technologies.)

The X axis of the surface shows the ratio of reads to writes and varies from 100% writes on the left to 100% reads on the right. The Y axis shows SSD performance in IOPS. The Z axis plots “block” size, from the SSD-level perspective (which is page size from the NAND Flash chip’s perspective, yes that’s confusing).

The first thing to note from this surface plot is that performance is a lot better on the right-hand side, which is dominated by reads. You’d expect that because SSD read performance is 10x better than SSD write performance. It’s the nature of NAND Flash memory. Note how fast the performance falls off as the percentage of write transactions increases. Then note that there’s a sort of saddle effect along the Z axis. The saddle peaks at 4-Kbyte blocks. Most SSD designs are optimized for 4-Kbyte blocks because most virtual operating systems employ 4-Kbyte blocks (and have for decades, in spite of the radical, orders-of-magnitude increase in memory use by both operating systems and application software).

So, clearly, when an SSD vendor gives an IOPS rating for an SSD, you need to take that one number with a grain of salt. SSD performance varies significantly depending on the read/write mix and on block size. Consequently, SSD performance can’t be captured in one or two numbers.

Next, Handy presented this graphic from SandForce (which makes SSD controller chips):

This graph shows an initial conditioning period during which the test preconditions (fills up) the SSD using sequential 128-Kbyte writes. The initial transfer performance (about 80 Mbytes/sec for the particular drive being tested) drops slightly as the drive fills and the internal SSD controller starts shuffling full NAND Flash blocks off to spare memory. The falloff isn’t big because the sequential writes place a predictable load on the SSD controller. However, when the test switches to random 4-Kbyte writes about 4000 seconds into the test, performance drops significantly because the SSD controller suddenly needs to make small changes to memory stored in the NAND Flash blocks but the drive’s full and there are no empty blocks. Blocks must be erased to make room for the new data and block erasure takes time. Consequently, there’s a big performance falloff as the controller starts to shuffle data around inside of the drive to make room for new data.

Perhaps more interesting is what happens when the test switches back to large sequential writes about 11,000 seconds into the test. Initially, the sequential writes cause the drive performance to vary wildly because the preceding random writes have scattered the spare blocks and left them distributed throughout the SSD’s internal NAND Flash memory space. Eventually, the SSD’s internal controller gets things sorted out and the performance for large sequential writes returns to the initial steady-state level.

(Note: This graph is not supposed to typify the performance of all SSDs. The graph shows the results of a test on one particular SSD.)

So what’s to be learned from all of this data? SSD performance measurement isn’t simple. Creating controllers and firmware that deliver optimum SSD performance isn’t simple either. As drive and chip vendors learn more about the use of NAND Flash for storage, they develop better algorithms for extracting more performance from the NAND Flash chips.

NAND Flash chips are complicated, whether used in SSDs or for server memory backup as with AgigA Tech’s AGIGARAM modules. It takes experience to get the most performance from these memory devices.

My thanks to Jim Handy for all of the great information in his Bell Micro keynote, and for generously letting me use the information in this series of blog entries.

First, take a look at this graphic depicting a “typical” server storage array consisting of 100 enterprise-class HDDs.

Each short-stroked, enterprise-class HDD has a capacity of 300 Gbytes, for a total array capacity of 30 Tbytes. This enterprise-class HDD array delivers 30K IOPS, costs $55,000, and consumes 1.75 kilowatts of electricity (not to mention an equivalent amount of electricity required for cooling). That’s the baseline.

Now look at this graphic, which compares the previously discussed array of enterprise-class HDDs with a hybrid array consisting of one SSD and 30 high-capacity, 1-Tbyte HDDs.

The high-capacity drives are not short-stroked, so they can provide a total storage capacity of 30T bytes with only 30 drives instead of 100 enterprise-class HDDs. However, the one SSD inserted into the drive array provides the same IOPS read performance as the 100 enterprise-class HDDs, so the use of the slower, less expensive, high-capacity HDDs in the second array is not a detriment to the second array’s IOPS performance, as long as the server software is written to make use of the hybrid array’s abilities.

The SSD-enhanced drive array costs $6040 or about 90% less than the array of 100 enterprise-class HDDs. The SSD-enhanced array consumes 0.392 kilowatts, which is nearly 80% less than the enterprise-class array of 100 short-stroked HDDs. Consequently, the second drive array generates substantially less waste heat (that must be cooled) than the full array of enterprise-class HDDs.

As a result, the SSD-enhanced drive array saves the enterprise customer a substantial amount of money when viewed from a systemic perspective. Relative to the enterprise-class HDD array, the SSD-enhanced hybrid drive array costs less to purchase; costs less to provision because fewer drives require less rack space and fewer racks; consume less electricity for operation; need less electricity for cooling because fewer, slower drives generate less heat; and reduce maintenance costs because the high-capacity drives run cooler (increasing MTBF), because there are fewer drives to maintain, and because high-capacity drives are much less expensive than enterprise-class drives. Overall, the TCO calculations favor the SSD-enhanced, hybrid drive array.

Handy took Sun’s numbers a step further by calculating the crossover point where TCO considerations favor an SSD-enhanced drive array over an array of enterprise-class HDDs when the IOPS performance is the main consideration rather than capacity. Here are Handy’s graphs:

The left graph shows price curves for an array of enterprise-class HDDs versus an array of SSDs. The array of SSDs initially costs more than the enterprise-class HDDs, so the crossover point is 1200 IOPS due to the high initial SSD cost. As the IOPS requirement rises, you need to add enterprise-class HDDs to the array to meet the higher IOPS requirements but one SSD gets you a lot of IOPS so there’s no need to add one until the IOPS requirement exceeds around 3000 IOPS. For the enterprise-class hybrid array, which mates one SSD with several high-capacity HDDs, the purchase cost of the SSD-enhanced array is much lower for a given capacity so the crossover point is also lower—just 400 IOPS.

TCO computations such as these are required for storage and for memory subsystems. It’s easy to be myopic and compare component cost to component cost, but system architects are creating systems and should always try to view component costs through a TCO lens.

You can see that from 2007 to 2008, NAND Flash pricing was in freefall and dropped from nearly $9/Gbyte to less than $2/Gbyte. This drop had two big effects. It hammered the NAND Flash vendors and it enticed a lot of companies to jump into the SSD market with visions of even cheaper NAND Flash chips on the horizon.

For now, it looks like NAND Flash pricing is on a more manageable price decline through 2012, at least according to this Forward Insights forecast. While this easing of the rate of price decline doesn’t bode well for those who look forward to large future price drops for SSDs, it provides hope for some bedrock stability for other NAND Flash applications such as AgigA Tech’s server-class, bulletproof AGIGARAM memory modules.

Why are the solid state disk drives still so expensive?

They are on the market for years and still so expensive. SSD of a reasonable capacity (256GB) costs as much as $800 or more. Aren’t they going to drop the prices?

Although the question appears to have been posed by someone not closely familiar with the ins and outs of hard-disk drive (HDD) and solid-state disk (SSD) technologies, markets, and pricing, it’s a frequent question posed by many in the industry. We’ve become so accustomed to large, regular drops in price/capacity for both mechanical storage (“rotating rust”) and semiconductor memory that we’ve collectively developed a sense of entitlement. If we can’t buy it today, we think, surely the price will drop and we’ll be able to afford it soon.

However, when we compare the price/capacity of SSDs against HDDs, we’re comparing one moving target against another. Moore’s Law governs the price of SSDs because the largest cost component in an SSD is NAND Flash memory (see below). Moore’s Law has been a monster force in the semiconductor industry, pushing prices ever lower for more than four decades. However, the HDD vendors are constantly working with their own price-reduction curve, which has proven to be just as robust as Moore’s Law. By pulling a veritable menagerie of rabbits out of various technological hats, HDD vendors have dropped per-bit pricing for HDDs about as fast as semiconductor vendors have cut the price/bit of NAND Flash memory.

Take a look at this graph from Handy’s keynote:

From the gross slopes of the two curves, you can see that HDD cost/capacity has remained about 20x lower than NAND Flash memory cost/capacity throughout this decade. Note that in 2006, there was a serious downturn in the slope of the curve for NAND Flash. Extrapolating that new slope led some to predict that NAND Flash cost/Gbyte would cross over that of HDDs by 2008 or 2009. That just didn’t happen. The increased rate of price decline was economically unsupportable and caused huge turmoil among NAND Flash vendors. (For extensive analysis of this situation, see this blog entry on Denali Software’s Web site.)

Now please understand, the expectation that NAND Flash cost/Gbyte would zoom past the HDD cost/Gbyte curve wasn’t just wishful thinking. NAND Flash per-bit costs did overtake and then zoom past that of DRAM, which was once the semiconductor industry’s king of cost/bit. That event happened in 2004 as shown in this slide from Handy’s keynote.

So the expectation that NAND Flash cost/bit would zoom past HDD cost/bit wasn’t at all far-fetched. It just didn’t happen. HDD vendors happily continued to cut the cost/bit of rotating storage, to the very great benefit of consumers and enterprise users everywhere.

Handy’s simple silicon anatomy of an SSD shows why the SSD’s cost/bit is closely tied to the cost of NAND Flash.

From a silicon perspective, Handy’s illustration shows 34 key semiconductor devices in his example 64-Gbyte SSD. Two of the devices are a controller chip and a DRAM buffer. Total cost for those two devices: $6. The other 32 devices are NAND Flash chips. Total cost for those devices: $64 for 64 Gbytes of storage (not counting spare capacity). The cost of the NAND Flash devices is more than 90% of the silicon cost of an SSD. The SSD’s price is largely set by the cost of its internal NAND Flash.

That’s why SSDs aren’t likely to replace HDDs for bulk storage in the foreseeable future. As long as the HDD industry has a road map leading to higher capacity and lower cost/bit storage, and it does, then the HDD will keep the throne as the storage capacity king.

SSDs can beat HDDs in raw performance by one or two orders of magnitude, as measured in IOPS. There’s nothing on the HDD road map that can change that situation. For applications that can measure the value of storage speed, and there are many such applications for enterprise-class storage, SSDs provide sufficient value to justify their higher price/bit. For most consumers, people who are selecting laptops for example, the choice between a 160-Gbyte HDD or a 32-Gbyte SSD for the same price is obvious. The consumer will choose more capacity (to store more music, more pictures, more video, and more movies) every time.

Now take a look at Handy’s curves for DRAM and NAND Flash cost/bit once again:

Note that the cost/bit of NAND Flash is now roughly 10% that of DRAM. That means that as a DRAM backup medium, NAND Flash doesn’t add that much to the cost of the DRAM it’s backing up. Unlike the comparison of NAND Flash and HDD capacity, which tilts far in favor of the HDD, NAND Flash densities are much better than DRAM bit densities and that gap is growing thanks to multi-level cell (MLC) storage. These economics are behind the idea for AgigA Tech’s AGIGARAM modules. For a small cost adder, volatile DRAM can be made bulletproof when paired with NAND Flash memory. For more detail regarding this idea, see the earlier 3-part series in this blog (here, here, and here).

For this blog entry, we’re returning to the Flash Zone, a concept described by Denali Software’s CTO Mark Gogolewski in his keynote speech—The World is Flash: A Disruption of the Memory & Storage Hierarchy—at Memcon 2009. The Flash Zone is the name put to the performance gap between DRAM and disk storage. There’s not only a gap in performance within the Flash Zone, there’s a transition from volatile memory (DRAM) to non-volatile storage (hard disk). With steep cost/bit price declines and per-device capacity growth, NAND Flash devices now easily fit into this gap and produce a new and viable layer in the overall computer memory hierarchy.

What’s new is that Jim Handy’s keynote at the Bell Micro SSD seminar put some welcome numbers on the Flash Zone that further clarify Flash’s place in the hierarchy. Here’s an image of that particular slide.

This image plots the performance and cost of the different memory hierarchy layers from first-, second-, and third-level processor cache through DRAM, disk, and tape. Because Handy’s used a log-log scale to plot everything, the graph looks nice and linear even though the reality is quite a bit messier. For a conceptual graph however, this’ll do nicely.

Note that there’s a gap in the hierarchy. That’s the Flash Zone. Here’s the same plot augmented a bit. The big red circle identifies the Flash Zone.

Also note that Handy has labeled the gap and says it’s “growing.” The gap’s growing because DRAM is getting faster, bigger, and cheaper, moving its ellipse up and to the left while HDDs are getting bigger, although not much faster, moving the HDD ellipse horizontally to the left. The result is a growing performance and bandwidth gap between DRAM and HDDs.

Flash fits into this gap very, very nicely said Handy (and as discussed in this blog previously). Later in his keynote, he displayed this image to underscore the point.

There are currently at least three ways to fill the Flash Zone in a memory hierarchy using NAND Flash memory. The first way, the way that gets the most attention these days, is with solid-state drives (SSDs). Because they employ the same interfaces and share the same form factor with HDDs, SSDs are an easy, drop-in Flash Zone filler. They boost performance just by dropping them into place as HDD replacements, although that may not be the best way to introduce SSDs into the hierarchy. (More about that in a later blog.)

The second way to drop NAND Flash memory into the Flash Zone is through direct- or I/O-attached drives. This is the approach advocated by Fusion-io, as discussed in that earlier AgigA Tech blog entry on the Flash Zone. Direct-attached SSDs eliminate the HDD interface and protocols, which were designed with built-in assumptions about the performance characteristics and limitations of HDDs (“rotating rust” quipped Scott Stetzer, VP of Marketing at SSD vendor STEC). Free of those limiting assumptions and limits, direct-attached SSDs deliver more performance than do SSDs employing HDD interfaces.

Handy showed the ways to introduce these two types of SSDs with the following slide:

In enterprise-class server systems, SSDs with HDD interfaces typically plug into SAN racks and tie to servers over a network while direct-attached SSDs plug directly into the server over a high-speed interface (typically PCIe). Note that smaller servers with HDD interfaces often talk to SSDs directly.

Because he was speaking at an SSD seminar, Handy did not discuss the third way of introducing NAND Flash into the Flash Zone—the approach employed by AgigA Tech’s AGIGARAM. That approach mates the NAND Flash directly to the server’s DRAM, creating a high-bandwidth connection between the two memory hierarchies. In this application, however, the NAND Flash is used for DRAM backup and power-failure bulletproofing—not necessarily for storage (although there are other possibilities to be discussed in this respect).

So far, we’ve only been able to discuss two of Handy’s 47 keynote slides. The talk contained a ton of good information for server designers and enterprise system architects. More later.

Note: Handy’s keynote was based on his company’s new report: Solid State Drives in the Enterprise – 2010.